Tag Archives: RISC-V

Project Open Se Cura Open Source Announcement

As AI permeates our lives, developing secure, scalable, and efficient compute systems is crucial for safe and trustworthy AI experiences. However, hardware advancements lag behind machine learning (ML) models and software development, hindering the deployment of secure and efficient full-stack systems. Furthermore, consumer demand for smaller devices outpaces battery technology advancements, constraining the power envelope and limiting the capabilities of deployable AI systems.

Towards these challenges, Google is launching Project Open Se Cura, an open-source framework to accelerate the development of secure, scalable, transparent and efficient AI systems. Previously known internally as Project Sparrow, Project Open Se Cura is a testament to our commitment to open-source development. Our goal with Open Se Cura is to evolve a set of open-source design tools and IP libraries that will accelerate the development of full-stack systems with ML workloads through co-design and development. This will enable us to better center system designs around security, efficiency, and scalability, empowering the next generation of AI experiences.

This work was developed in close collaboration with our partners such as lowRISC, Antmicro and VeriSilicon for key parts of the tooling and infrastructure. lowRISC has contributed a transparent root of trust, along with development and integration tools, ensuring a secure foundation for the project. Antmicro has contributed system simulation tooling with Renode and expertise in open-source system-level software. VeriSilicon has contributed expertise in IP design, silicon design, BSP development and commercialization. And together, we’ve used these tools for the first time to extend our IP library with secure ML capabilities and generated a proof of concept for a low-power AI system.

To accelerate open development and transparency of AI system design, we’re releasing our entire code base for developers to consider -- you can get started by following the instructions in the README.md.

Going forward, we’ll continue to evolve Open Se Cura in the open and seek to onboard additional partners, such as Cambridge University (for CHERI innovations) and the University of Michigan (for low-power and generative AI). We are excited to explore what we can build with these new tools and hope the open source community will join us and contribute.

We look forward to working with the open-source community to drive new innovations and new AI experiences with secure, scalable and efficient ML systems.

Join us and our partners, Brian Murray from VeriSilicon and Michael Gielda from Antmicro, for a technical deep dive at the CHIPS Alliance Technology Update. This hybrid workshop event will be held from 9:10 to 10:00 AM PST on November 9th at Google's Sunnyvale office.

By Kai Yick – Research Cerebra Open Source team

Android and RISC-V: What you need to know to be ready

Android is an open source operating system that is freely available to port to many devices and architectures. As such it supports many different device types and CPU architectures. We’re excited to be adding a new one to that list - RISC-V.

RISC-V is a free and open instruction set architecture (ISA), bringing the same spirit of industry-wide collaboration and innovation that we see in software around open source to the hardware ecosystem. Invented 10 years ago at the University of California, Berkeley, RISC-V has seen rapid adoption in embedded and microcontroller spaces, and in recent years has expanded into accelerators, servers, and mobile computing.

In November of 2022, we announced at the RISC-V Summit that we were accepting patches for RISC-V:

The latest update that we have is that now not only are we accepting patches, but we have begun to mature support for RISC-V in Android. RISC-V is a modular ISA, meaning that there are a large number of optional extensions. We have also determined an initial set that we feel is critical to ensure that any CPU running RISC-V will have all of the features we expect to achieve high performance. This set includes the rva22 profile as well as the vector and vector crypto extensions. This update was provided at the RISC-V summit in Europe:

You can build, test, and run the Android support for RISC-V on your own machine as well now! Just like other platform targets in AOSP, you can use the Cuttlefish Virtual Device support:

$ lunch aosp_cf_riscv64_phone-userdebug $ m -j $ launch_cvd -cpus=8 -memory_mb=8192

Then, you can use vncviewer to connect to the running device and interact.

Moving image of vncviewer running on an Android device

At this time, these patches will support building and running a basic Android Open Source Project experience, but are not yet fully optimized. For example, work on a fully optimized backend for the Android Runtime (ART) is still a work in progress. Additionally, AOSP, our external projects, and compilers haven’t generated fully optimized, reduced code that also takes advantage of the latest ratified extensions, such as the one for vectors. However, we believe that it is ready to allow experimentation and collaboration.

Later this year, we expect to have the NDK ABI finalized and canary builds available on Android’s public CI soon and RISC-V on x86-64 & ARM64 available for easier testing of riscv64 Android applications on a host machine. By 2024, the plan is to have emulators available publicly, with a full feature set to test applications for various device form factors! As recently announced in our collaboration with Qualcomm, we expect wearables to be the first form factor available.

However, just porting the Android operating system itself is not enough! We are working with the community and RISE (RISC-V Software Ecosystem). The RISE Project has been established to provide a way to accelerate the availability of software for high-performance and power-efficient RISC-V processor cores running high-level operating systems. That includes not only Android, but also Linux and other operating systems across a variety of application domains, including high-performance computing. The RISE Project includes members from Andes, Google, Intel, Imagination Technologies, MediaTek, Nvidia, Qualcomm Technologies, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana.

Google is also continuing and expanding our strong investments at RISC-V International, even beyond our long-standing Premium membership and board participation. We also have many other contributors in key roles on horizontal committees, working groups, and technical committees to ensure that specifications are rapidly being designed and ratified to benefit not only Android but also many other use cases.

Android's support for RISC-V is dependent on a wide range of contributions from toolchain to basic support libraries. We are very appreciative of the ongoing efforts which requires countless projects to support RISC-V build configurations and quality implementations. If you are interested in contributing please visit the following resources:

  • https://github.com/google/android-riscv64 for detailed information on how to build and test the RISC-V support in Android, list of known issues and opportunities to contribute to AOSP at source.android.com and toolchain projects and support libraries.
  • Subscribe to RISC-V Android SIG mailing list or join directly, if your organization is a member of RISC-V International to stay tuned in to progress and offer your suggestions and feedback.

Make sure to stay tuned as we look into ways to make it as easy for Android developers writing native to target new platforms as it is for our Java and Kotlin developers!

Planning to head to the RISC-V International Summit in November? Find us there– we’ll be hosting a Community Collaboration Breakfast on Wednesday morning! Not attending the conference but interested? Learn more and register here.

By Lars Bergstrom – Android Platform Programming Languages & Greg Simon - Google Low-level Operating System

Android and RISC-V: What you need to know to be ready

Android is an open source operating system that is freely available to port to many devices and architectures. As such it supports many different device types and CPU architectures. We’re excited to be adding a new one to that list - RISC-V.

RISC-V is a free and open instruction set architecture (ISA), bringing the same spirit of industry-wide collaboration and innovation that we see in software around open source to the hardware ecosystem. Invented 10 years ago at the University of California, Berkeley, RISC-V has seen rapid adoption in embedded and microcontroller spaces, and in recent years has expanded into accelerators, servers, and mobile computing.

In November of 2022, we announced at the RISC-V Summit that we were accepting patches for RISC-V:

The latest update that we have is that now not only are we accepting patches, but we have begun to mature support for RISC-V in Android. RISC-V is a modular ISA, meaning that there are a large number of optional extensions. We have also determined an initial set that we feel is critical to ensure that any CPU running RISC-V will have all of the features we expect to achieve high performance. This set includes the rva22 profile as well as the vector and vector crypto extensions. This update was provided at the RISC-V summit in Europe:

You can build, test, and run the Android support for RISC-V on your own machine as well now! Just like other platform targets in AOSP, you can use the Cuttlefish Virtual Device support:

$ lunch aosp_cf_riscv64_phone-userdebug $ m -j $ launch_cvd -cpus=8 -memory_mb=8192

Then, you can use vncviewer to connect to the running device and interact.

Moving image of vncviewer running on an Android device

At this time, these patches will support building and running a basic Android Open Source Project experience, but are not yet fully optimized. For example, work on a fully optimized backend for the Android Runtime (ART) is still a work in progress. Additionally, AOSP, our external projects, and compilers haven’t generated fully optimized, reduced code that also takes advantage of the latest ratified extensions, such as the one for vectors. However, we believe that it is ready to allow experimentation and collaboration.

Later this year, we expect to have the NDK ABI finalized and canary builds available on Android’s public CI soon and RISC-V on x86-64 & ARM64 available for easier testing of riscv64 Android applications on a host machine. By 2024, the plan is to have emulators available publicly, with a full feature set to test applications for various device form factors! As recently announced in our collaboration with Qualcomm, we expect wearables to be the first form factor available.

However, just porting the Android operating system itself is not enough! We are working with the community and RISE (RISC-V Software Ecosystem). The RISE Project has been established to provide a way to accelerate the availability of software for high-performance and power-efficient RISC-V processor cores running high-level operating systems. That includes not only Android, but also Linux and other operating systems across a variety of application domains, including high-performance computing. The RISE Project includes members from Andes, Google, Intel, Imagination Technologies, MediaTek, Nvidia, Qualcomm Technologies, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana.

Google is also continuing and expanding our strong investments at RISC-V International, even beyond our long-standing Premium membership and board participation. We also have many other contributors in key roles on horizontal committees, working groups, and technical committees to ensure that specifications are rapidly being designed and ratified to benefit not only Android but also many other use cases.

Android's support for RISC-V is dependent on a wide range of contributions from toolchain to basic support libraries. We are very appreciative of the ongoing efforts which requires countless projects to support RISC-V build configurations and quality implementations. If you are interested in contributing please visit the following resources:

  • https://github.com/google/android-riscv64 for detailed information on how to build and test the RISC-V support in Android, list of known issues and opportunities to contribute to AOSP at source.android.com and toolchain projects and support libraries.
  • Subscribe to RISC-V Android SIG mailing list or join directly, if your organization is a member of RISC-V International to stay tuned in to progress and offer your suggestions and feedback.

Make sure to stay tuned as we look into ways to make it as easy for Android developers writing native to target new platforms as it is for our Java and Kotlin developers!

Planning to head to the RISC-V International Summit in November? Find us there– we’ll be hosting a Community Collaboration Breakfast on Wednesday morning! Not attending the conference but interested? Learn more and register here.

By Lars Bergstrom – Android Platform Programming Languages & Greg Simon - Google Low-level Operating System

OpenTitan at one year: the open source journey to secure silicon

During the past year, OpenTitan has grown tremendously as an open source project and is on track to provide transparent, trustworthy, and cost-free security to the broader silicon ecosystem. OpenTitan, the industry’s first open source silicon root of trust, has rapidly increased engineering contributions, added critical new partners, selected our first tapeout target, and published a comprehensive logical security model for the OpenTitan silicon, among other accomplishments.

OpenTitan by the Numbers

OpenTitan has doubled many metrics in the year since our public launch: in design size, verification testing, software test suites, documentation, and unique collaborators at least. Crucially, this growth has been both in the design verification collateral required for high volume production-quality silicon, as well as the digital design itself, a first for any open source silicon project.
  • More than doubled the number of commits at launch: from 2,500 to over 6,100 (across OpenTitan and the Ibex RISC-V core sub-project).
  • Grew to over 141K lines of code (LOC) of System Verilog digital design and verification.
  • Added 13 new IP blocks to grow to a total to 29 distinct hardware units.
  • Implemented 14 Device Interface Functions (DIFs) for a total 15 KLOC of C11 source code and 8 KLOC of test software.
  • Increased our design verification suite to over 66,000 lines of test code for all IP blocks.
  • Expanded documentation to over 35,000 lines of Markdown.
  • Accepted contributions from 52 new unique contributors, bringing our total to 100.
  • Increased community presence as shown by an aggregate of over 1,200 Github stars between OpenTitan and Ibex.
Chart that shows: One year of OpenTitan and Ibex growth on GitHub: the total number of commits grew from 2,500 to over 6,100
One year of OpenTitan and Ibex growth on GitHub: the total number of commits grew from 2,500 to over 6,100.
High quality development is one of OpenTitan’s core principles. Besides our many style guides, we require thorough documentation and design verification for each IP block. Each piece of hardware starts with auto-generated documentation to ensure consistency between documentation and design, along with extensive, progressively improving, design verification as it advances through the OpenTitan hardware stages to reach tapeout readiness.
One year of growth in Design Verification: from 30,000 to over 65,000 lines of testing source code. Each color represents design verification for an individual IP block.

Innovating for Open Silicon Development

Besides writing code, we have made significant advances in developing processes and security framework for high quality, secure open source silicon development. Design success is not just measured by the hardware, highly functional software and a firm contract between the two, with well-defined interfaces and well-understood behavior, play an important role.

OpenTitan’s hardware-software contract is realized by our DIF methodology, yet another way in which we ensure hardware IP quality. DIFs are a form of hardware-software co-design and the basis of our chip-level design verification testing infrastructure. Each OpenTitan IP block requires a style guide-compliant DIF, and this year we implemented 14 DIFs for a total 15 KLOC of C11 source code and 8 KLOC of tests.

We also reached a major milestone by publishing an open Security Model for a silicon root of trust, an industry first. This comprehensive guidance demonstrates how OpenTitan provides the core security properties required of a secure root of trust. It covers provisioning, secure boot, device identity, and attestation, and our ownership transfer mechanism, among other topics.

Expanding the OpenTitan Ecosystem

Besides engineering effort and methodology development, the OpenTitan coalition added two new Steering Committee members in support of lowRISC as an open source not-for-profit organization. Seagate, a leader in storage technology, and Giesecke and Devrient Mobile Security, a major producer of certified secure systems. We also chartered our Technical Committee to steer technical development of the project. Technical Committee members are drawn from across our organizational and individual contributors, approving 9 technical RFCs and adding 11 new project committers this past year.

On the strength of the OpenTitan open source project’s engineering progress, we are excited to announce today that Nuvoton and Google are collaborating on the first discrete OpenTitan silicon product. Much like the Linux kernel is itself not a complete operating system, OpenTitan’s open source design must be instantiated in a larger, complete piece of silicon. We look forward to sharing more on the industry’s first open source root of trust silicon tapeout in the coming months.

Onward to 2021

OpenTitan’s future is bright, and as a project it fully demonstrates the potential for open source design to enable collaboration across disparate, geographically far flung teams and organizations, to enhance security through transparency, and enable innovation in the open. We could not do this without our committed project partners and supporters, to whom we owe all this progress: Giesecke and Devrient Mobile Security, Western Digital, Seagate, the lowRISC CIC, Nuvoton, ETH Zürich, and many independent contributors.

Interested in contributing to the industry's first open source silicon root of trust? Contact us here.

By Dominic Rizzo, OpenTitan Lead – Google Cloud